{"id":1814,"date":"2026-07-21T15:54:28","date_gmt":"2026-07-21T22:54:28","guid":{"rendered":"https:\/\/nanzhou.cc\/?p=1814"},"modified":"2026-07-21T15:54:28","modified_gmt":"2026-07-21T22:54:28","slug":"pcie-basics","status":"publish","type":"post","link":"https:\/\/nanzhou.cc\/index.php\/2026\/07\/21\/pcie-basics\/","title":{"rendered":"PCIe Basics"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">1. The Evolutionary Leap: From PCI to PCIe<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">In the 1990s and early 2000s, motherboards relied on&nbsp;<strong>PCI<\/strong>&nbsp;and&nbsp;<strong>PCI-X<\/strong>&nbsp;(PCI Extended). These were&nbsp;<strong>shared parallel buses<\/strong>, meaning multiple devices were connected to the same set of physical wires.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">The Parallel Bottleneck<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">While intuitive, parallel buses hit a hard physical limit as clock speeds increased:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Clock Skew<\/strong>: Since signals travel down 32 or 64 individual copper traces, tiny variations in trace length meant bits would arrive at slightly different times, corrupting data.<\/li>\n\n\n\n<li><strong>Shared Bandwidth<\/strong>: If one PCI device was hogging the bus, other devices had to wait, severely limiting system throughput.<\/li>\n\n\n\n<li><strong>Bulky Routing<\/strong>: Routing dozens of parallel traces made motherboard design incredibly complex and pin-heavy.<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">The PCIe Paradigm Shift (2003)<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">To break this bottleneck, a coalition of industry leaders introduced&nbsp;<strong>PCI Express (3GIO)<\/strong>&nbsp;in 2003. PCIe threw out the parallel model and replaced it with a&nbsp;<strong>point-to-point, serial packet-based topology<\/strong>:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Dedicated Lanes<\/strong>: Instead of sharing a bus, every device gets its own direct link to the Root Complex (CPU\/Chipset).<\/li>\n\n\n\n<li><strong>Dual-Simplex Serial Pairs<\/strong>: Each lane consists of two differential copper wire pairs\u2014one for transmitting (Tx) and one for receiving (Rx).<\/li>\n\n\n\n<li><strong>Scalability<\/strong>: Lanes can be grouped together (x1, x4, x8, x16) to scale bandwidth for demanding hardware like GPUs.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">2. The PCIe Generational Roadmap<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">With every new generation, the PCIe standard has successfully doubled its bandwidth. This required switching from traditional&nbsp;<strong>NRZ (Non-Return-to-Zero)<\/strong>&nbsp;signaling to&nbsp;<strong>PAM4 (Pulse Amplitude Modulation 4-Level)<\/strong>&nbsp;in Gen 6 to pack more data into the same physical frequencies.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Gen<\/th><th>Year<\/th><th>Transfer Rate<\/th><th>Line Encoding<\/th><th>Bandwidth per Lane (x1)<\/th><\/tr><tr><td><strong>Gen 1<\/strong><\/td><td>2003<\/td><td>2.5 GT\/s<\/td><td>8b\/10b (20% overhead)<\/td><td>~250 MB\/s<\/td><\/tr><tr><td><strong>Gen 2<\/strong><\/td><td>2007<\/td><td>5.0 GT\/s<\/td><td>8b\/10b (20% overhead)<\/td><td>~500 MB\/s<\/td><\/tr><tr><td><strong>Gen 3<\/strong><\/td><td>2010<\/td><td>8.0 GT\/s<\/td><td>128b\/130b (~1.5% overhead)<\/td><td>~1 GB\/s<\/td><\/tr><tr><td><strong>Gen 4<\/strong><\/td><td>2017<\/td><td>16.0 GT\/s<\/td><td>128b\/130b (~1.5% overhead)<\/td><td>~2 GB\/s<\/td><\/tr><tr><td><strong>Gen 5<\/strong><\/td><td>2019<\/td><td>32.0 GT\/s<\/td><td>128b\/130b (~1.5% overhead)<\/td><td>~4 GB\/s<\/td><\/tr><tr><td><strong>Gen 6<\/strong><\/td><td>2022<\/td><td>64.0 GT\/s<\/td><td>PAM4 \/ FLIT (~1.5% overhead)<\/td><td>~8 GB\/s<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">3. Core Infrastructure: Who&#8217;s Talking?<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">A physical PCIe link consists of three primary components in a point-to-point hierarchy:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Component<\/th><th>Role in the Link<\/th><th>Key Hardware Detail<\/th><\/tr><tr><td><strong>Root Complex<\/strong><\/td><td>The root host bridge connecting the CPU and memory to the PCIe fabric.<\/td><td>Can be integrated directly into the CPU die or exist as a discrete chipset.<\/td><\/tr><tr><td><strong>Repeater<\/strong><\/td><td>Active signal conditioning devices placed along long motherboard traces.<\/td><td>Divided into&nbsp;<strong>Redrivers<\/strong>&nbsp;(analog amplifiers) and&nbsp;<strong>Retimers<\/strong>&nbsp;(re-clocking digital chips).<\/td><\/tr><tr><td><strong>Endpoint<\/strong><\/td><td>The downstream peripheral device receiving\/sending the payload.<\/td><td>Can be physical cards (GPUs), M.2 SSDs, or integrated onboard controllers.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h2 class=\"wp-block-heading\">4. Side-Band Signaling: The Ignition Keys<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Before high-speed serial lanes can transmit data, a set of crucial auxiliary control signals must stabilize.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Signal Name<\/th><th>Active State<\/th><th>Purpose<\/th><\/tr><tr><td><strong>PERST#<\/strong><\/td><td>Active Low<\/td><td><strong>Fundamental Reset<\/strong>. It must be held low until system power rails and reference clocks are completely stable. Transitioning to high begins link initialization.<\/td><\/tr><tr><td><strong>WAKE#<\/strong><\/td><td>Active Low<\/td><td><strong>Wakeup request<\/strong>. Signals transitions from low-power sleep states back to active states.<\/td><\/tr><tr><td><strong>CLKREQ#<\/strong><\/td><td>Active Low<\/td><td><strong>Clock Request<\/strong>. Used by endpoints to request that the reference clock be enabled or disabled to conserve power.<\/td><\/tr><tr><td><strong>REFCLK<\/strong><\/td><td>100 MHz clock<\/td><td><strong>Reference Clock<\/strong>. A shared, stable clock signal that both devices use to generate their internal high-speed transmit clocks.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<h2 class=\"wp-block-heading\">5. The 3-Step Link Training Process<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">Once&nbsp;<code>PERST\\#<\/code>&nbsp;is released and&nbsp;<code>REFCLK<\/code>&nbsp;is stable, the hardware triggers the&nbsp;<strong>Link Training and Status State Machine (LTSSM)<\/strong>. This establishes the initial link at Gen 1 speeds (2.5 Gbps) using three logical phases:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code class=\"\">  [1. Rx Detect]         [2. Polling]         [3. Configuration]\n  (Detect partner)  --&gt;  (Lock clocks)   --&gt;  (Deskew &amp; lane assignment)\n<\/code><\/pre>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Phase<\/th><th>What Happens<\/th><th>Signal Mechanics<\/th><\/tr><tr><td><strong>1. Rx Detect<\/strong><\/td><td>The transmitter checks if a physical receiver is attached on the other side of the lane.<\/td><td>The Tx circuit charges a capacitor on the line and measures the rate of charge to detect the receiver&#8217;s presence.<\/td><\/tr><tr><td><strong>2. Polling<\/strong><\/td><td>Both sides exchange continuous patterns to sync up their clocks and decoders.<\/td><td>Devices transmit&nbsp;<strong>Training Sequences<\/strong>&nbsp;(TS1\/TS2) to establish&nbsp;<strong>Bit Lock<\/strong>&nbsp;(frequency synchronization) and&nbsp;<strong>Symbol Lock<\/strong>&nbsp;(aligning 10-bit patterns).<\/td><\/tr><tr><td><strong>3. Configuration<\/strong><\/td><td>The link compensates for physical trace length variances and assigns lane numbers.<\/td><td>Operates a&nbsp;<strong>lane-to-lane deskew<\/strong>&nbsp;to align arriving signals. Determines&nbsp;<strong>link width<\/strong>&nbsp;(e.g., x1, x4, x8, x16) and handles any&nbsp;<strong>bifurcation<\/strong>&nbsp;(splitting lanes across multiple devices).<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">After completing&nbsp;<strong>Configuration<\/strong>, the link enters the&nbsp;<strong>L0 state<\/strong>\u2014the fully active, normal operational state.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">6. Link Equalization: Fine-Tuning Gen 3 and Beyond<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">At speeds of Gen 3 (8 GT\/s) and higher, standard FR4 motherboard copper traces act like low-pass filters, severely distorting high-frequency signals. To combat this, devices must run&nbsp;<strong>Link Equalization<\/strong>, adjusting transmitter waveforms using predefined&nbsp;<strong>Presets (numbered 0 to 10)<\/strong>.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">If you have a Gen 5 link, the hardware must step up through&nbsp;<strong>three consecutive equalization cycles<\/strong>: Gen 1 \u2794 Gen 3, Gen 3 \u2794 Gen 4, and finally Gen 4 \u2794 Gen 5. Each cycle runs through four distinct phases:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code class=\"\"> [Phase 0: Preset Request] \u2794 [Phase 1: Coarse Sync] \u2794 [Phase 2: Upstream Fine-Tune] \u2794 [Phase 3: Downstream Fine-Tune]\n<\/code><\/pre>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Phase 0 &amp; 1: Coarse Negotiation<\/strong>: The downstream port requests its desired transmitter presets from the upstream device. The link steps up to the target speed and repeatedly exchanges training sequences to guarantee a basic Bit Error Rate (BER) of less than $10^{-4}$.<\/li>\n\n\n\n<li><strong>Phase 2 &amp; 3: Deep Optimization<\/strong>: The link runs a fine-tuning protocol. Phase 2 optimizes the transmitter settings of the upstream port, and Phase 3 optimizes the downstream port. By the end of Phase 3, the transceiver waveforms are perfectly tuned, achieving a reliable target Bit Error Rate (BER) of less than $10^{-12}$.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">7. Signal Integrity Bottlenecks: Redrivers vs. Retimers<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">As bus speeds double with every generation, physical trace length on motherboards becomes your worst enemy. If your traces are too long, even maximum preset adjustments in Link Equalization cannot achieve a stable link. Designers must use&nbsp;<strong>Repeaters<\/strong>&nbsp;to extend the signal:<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Feature<\/th><th>Redriver<\/th><th>Retimer<\/th><\/tr><tr><td><strong>Primary Technology<\/strong><\/td><td>Pure analog amplifier \/ equalizer.<\/td><td>Mixed-signal digital transceiver.<\/td><\/tr><tr><td><strong>Latency<\/strong><\/td><td>Extremely low (hundreds of picoseconds).<\/td><td>Moderate (buffers and re-clocks the signal).<\/td><\/tr><tr><td><strong>Signal Cleansing<\/strong><\/td><td>Amplifies both the signal&nbsp;<strong>and<\/strong>&nbsp;the background noise.<\/td><td>Fully extracts data, eliminates jitter, and re-transmits a fresh, clean signal.<\/td><\/tr><tr><td><strong>Cost &amp; Complexity<\/strong><\/td><td>Low cost, simple trace layout.<\/td><td>Higher cost, requires firmware and register configurations.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">Using retimers is virtually mandatory for Gen 5 and Gen 6 system architectures to successfully span across motherboards to external risers or dense server backplanes!<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">8. Pinout<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\">\u00a0A standard PCI Express card edge connector has a standardized pinout divided into two physical sides\u00a0<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Side A (Back \/ Solder Side)<\/strong><\/li>\n\n\n\n<li><strong>Side B (Front \/ Component Side)<\/strong>\u00a0<a href=\"https:\/\/knightli.com\/en\/2022\/05\/15\/pci-express-pinout\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">The connector is split by a physical\u00a0<strong>keying notch<\/strong>\u00a0that separates the\u00a0<strong>Power and Management Section<\/strong>\u00a0(Pins 1\u201311) from the\u00a0<strong>High-Speed Data Lanes<\/strong>\u00a0(Pins 12 and beyond). This ensures you cannot insert a card backward.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Below is the complete, standard PCIe wiring pinout, followed by the external power connector layouts&nbsp;<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Power &amp; System Management Pins (Pins 1\u201311)<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\"><em class=\"\">Located before the physical mechanical key notch&nbsp;<\/em><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">These pins are identical across all slot sizes (x1, x4, x8, x16)\u00a0<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Pin #<\/th><th>Side B (Component Side)<\/th><th>Side A (Solder Side)<\/th><th>Signal Description<\/th><\/tr><tr><td><strong>1<\/strong><\/td><td><code>+12 V<\/code>&nbsp;<a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/td><td><code>PRSNT1#<\/code>&nbsp;(Hot-plug detect)&nbsp;<a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/td><td>Powers the card; detects if card is fully plugged in&nbsp;<a href=\"https:\/\/knightli.com\/en\/2022\/05\/15\/pci-express-pinout\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;.<\/td><\/tr><tr><td><strong>2<\/strong><\/td><td><code>+12 V<\/code><\/td><td><code>+12 V<\/code><\/td><td>Main power supply line.<\/td><\/tr><tr><td><strong>3<\/strong><\/td><td><code>+12 V<\/code><\/td><td><code>+12 V<\/code><\/td><td>Main power supply line&nbsp;<a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;.<\/td><\/tr><tr><td><strong>4<\/strong><\/td><td><code>GND<\/code><\/td><td><code>GND<\/code><\/td><td>Ground reference.<\/td><\/tr><tr><td><strong>5<\/strong><\/td><td><code>SMCLK<\/code><\/td><td><code>TCK<\/code><\/td><td>SMBus Clock (B) \/ JTAG Clock (A).<\/td><\/tr><tr><td><strong>6<\/strong><\/td><td><code>SMDAT<\/code><\/td><td><code>TDI<\/code><\/td><td>SMBus Data (B) \/ JTAG Data In (A).<\/td><\/tr><tr><td><strong>7<\/strong><\/td><td><code>GND<\/code><\/td><td><code>TDO<\/code><\/td><td>Ground (B) \/ JTAG Data Out (A)&nbsp;<a href=\"https:\/\/www.scribd.com\/document\/654863640\/PCIe-CEM-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;.<\/td><\/tr><tr><td><strong>8<\/strong><\/td><td><code>+3.3 V<\/code><\/td><td><code>TMS<\/code><\/td><td>Auxiliary 3.3V power (B) \/ JTAG Mode Select (A).<\/td><\/tr><tr><td><strong>9<\/strong><\/td><td><code>TRST#<\/code><\/td><td><code>+3.3 V<\/code><\/td><td>JTAG Reset (B) \/ Standard 3.3V power (A).<\/td><\/tr><tr><td><strong>10<\/strong><\/td><td><code>+3.3 Vaux<\/code><\/td><td><code>+3.3 V<\/code><\/td><td>Standby power (B) \/ Standard 3.3V power (A)&nbsp;<a href=\"https:\/\/en.wikipedia.org\/wiki\/PCI_Express\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;.<\/td><\/tr><tr><td><strong>11<\/strong><\/td><td><code>WAKE#<\/code>&nbsp;<a href=\"https:\/\/knightli.com\/en\/2022\/05\/15\/pci-express-pinout\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/td><td><code>PERST#<\/code>&nbsp;<a href=\"https:\/\/allpinouts.org\/pinouts\/connectors\/buses\/pci-express-8x\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/td><td>Link Wakeup (B)&nbsp;<a href=\"https:\/\/knightli.com\/en\/2022\/05\/15\/pci-express-pinout\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;\/ Fundamental Reset (A)&nbsp;<a href=\"https:\/\/allpinouts.org\/pinouts\/connectors\/buses\/pci-express-8x\/\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>&nbsp;.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">\ud83d\udd11&nbsp;<strong>The Keying Notch sits right here (between Pins 11 and 12)<\/strong>&nbsp;<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">High-Speed Data Lanes (Pins 12\u201382)<\/h3>\n\n\n\n<p class=\"wp-block-paragraph\"><em>All high-speed lanes consist of differential pairs for Transmit (<code>TX<\/code>\/<code>HSOp<\/code>\/<code>HSOn<\/code>) and Receive (<code>RX<\/code>\/<code>HSIp<\/code>\/<code>HSIn<\/code>)&nbsp;<\/em><em><a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a><\/em>&nbsp;.&nbsp;To prevent noise and crosstalk, every single high-speed pair is separated by a dedicated&nbsp;<code>GND<\/code>&nbsp;(Ground) pin&nbsp;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Depending on the slot size, the pins terminate at different lengths:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>x1 Slot<\/strong>: Terminated at Pin 18<\/li>\n\n\n\n<li><strong>x4 Slot<\/strong>: Terminated at Pin 32<\/li>\n\n\n\n<li><strong>x8 Slot<\/strong>: Terminated at Pin 49<\/li>\n\n\n\n<li><strong>x16 Slot<\/strong>: Terminated at Pin 82<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\">First Data Lane (Lane 0) Details:<\/h4>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><tbody><tr><th>Pin #<\/th><th>Side B (Component Side)<\/th><th>Side A (Solder Side)<\/th><th>Signal Description<\/th><\/tr><tr><td><strong>12<\/strong><\/td><td><code>GND<\/code><\/td><td><code>REFCLK+<\/code><\/td><td>Ground (B) \/ Reference Clock + (A).<\/td><\/tr><tr><td><strong>13<\/strong><\/td><td><code>GND<\/code><\/td><td><code>REFCLK-<\/code><\/td><td>Ground (B) \/ Reference Clock &#8211; (A).<\/td><\/tr><tr><td><strong>14<\/strong><\/td><td><code>HSOp(0)<\/code>&nbsp;(Tx+)<\/td><td><code>GND<\/code><\/td><td>Lane 0 Transmitter (B) \/ Ground (A).<\/td><\/tr><tr><td><strong>15<\/strong><\/td><td><code>HSOn(0)<\/code>&nbsp;(Tx-)<\/td><td><code>GND<\/code><\/td><td>Lane 0 Transmitter (B) \/ Ground (A).<\/td><\/tr><tr><td><strong>16<\/strong><\/td><td><code>GND<\/code><\/td><td><code>HSIp(0)<\/code>&nbsp;(Rx+)<\/td><td>Ground (B) \/ Lane 0 Receiver (A).<\/td><\/tr><tr><td><strong>17<\/strong><\/td><td><code>GND<\/code><\/td><td><code>HSIn(0)<\/code>&nbsp;(Rx-)<\/td><td>Ground (B) \/ Lane 0 Receiver (A).<\/td><\/tr><tr><td><strong>18<\/strong><\/td><td><code>GND<\/code><\/td><td><code>GND<\/code><\/td><td>Ground.&nbsp;<strong>(x1 Slot Ends Here)<\/strong><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<h4 class=\"wp-block-heading\">The Repeating Data Pattern:<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Beyond Pin 18, the lanes repeat a highly predictable geometric pattern:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Side B<\/strong>\u00a0always hosts the\u00a0<strong>Transmitter (Tx)<\/strong>\u00a0signals.<\/li>\n\n\n\n<li><strong>Side A<\/strong>\u00a0always hosts the\u00a0<strong>Receiver (Rx)<\/strong>\u00a0signals\u00a0<a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>\u00a0.<\/li>\n\n\n\n<li>The system repeats:\u00a0<code>GND<\/code>\u00a0\u2794\u00a0<code>Tx+<\/code>\/<code>Tx-<\/code>\u00a0(Side B) or\u00a0<code>Rx+<\/code>\/<code>Rx-<\/code>\u00a0(Side A) \u2794\u00a0<code>GND<\/code>\u00a0<a href=\"https:\/\/www.scribd.com\/document\/733389549\/PCIE-X16-Pinout\" target=\"_blank\" rel=\"noreferrer noopener\"><\/a>\u00a0.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Reference<\/h2>\n\n\n\n<p class=\"wp-block-paragraph\"><a href=\"https:\/\/www.ti.com\/lit\/an\/snla415\/snla415.pdf?ts=1784569924417\">https:\/\/www.ti.com\/lit\/an\/snla415\/snla415.pdf?ts=1784569924417<\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p>1. The Evolutionary Leap: From PCI to PCIe In the 1990s and early 2000s, motherboards relied on&nbsp;PCI&nbsp;and&nbsp;PCI-X&nbsp;(PCI Extended). These were&nbsp;shared parallel buses, meaning multiple devices were connected to the same set of physical wires. The Parallel Bottleneck While intuitive, parallel buses hit a hard physical limit as clock speeds increased: The PCIe Paradigm Shift (2003)&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"0","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[76],"tags":[],"class_list":["post-1814","post","type-post","status-publish","format-standard","hentry","category-embedded"],"_links":{"self":[{"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/posts\/1814","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/comments?post=1814"}],"version-history":[{"count":1,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/posts\/1814\/revisions"}],"predecessor-version":[{"id":1815,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/posts\/1814\/revisions\/1815"}],"wp:attachment":[{"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/media?parent=1814"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/categories?post=1814"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/nanzhou.cc\/index.php\/wp-json\/wp\/v2\/tags?post=1814"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}